1. Field of the Invention
The present invention relates to a PLL circuit, its automatic adjusting circuit, and a semiconductor device including same.
2. Description of the Related Art
A PLL circuit is used, for example, as a circuit to extract a clock signal from a serial signal in a receiver. The free running frequency of a VCO in the PLL circuit generally differs between semiconductor chips even if made from the same wafer because there is often a slight variation in the manufacturing process of semiconductor devices, varying the free running frequency about .+-.30 percent. Therefore, a PLL circuit with a wide capture range is required, and the circuit design therefore becomes complicated or difficult.
With this, a digital VCO with a variable center frequency setting is used for the PLL circuit as shown in FIG. 9. In this circuit, a phase comparator 10, a loop filter 11, a VCO control circuit 12, and a digital VCO 13 are connected in the loop shape.
The VCO control circuit 12 is a kind of analog to digital converter and outputs the digital value DV corresponding to the analog voltage AV. FIG. 10(A) shows the input-output characteristics of the VCO control circuit 12.
The frequency f of the output clock CLK from the digital VCO 13 is a linear function of the digital value DV. f/fc varies with the digital value DV as shown in FIG. 10(B), where fc is a center frequency at the digital value DV being a half of the maximum frequency value DVmax. The center frequency fc is determined by the center frequency setting value CFV from the center frequency setting circuit 14. fc/fco varies as shown in FIG. 10(C), where fco is a center free running frequency at the center frequency setting value CFV being a half of the maximum value CFVmax thereof. In this example, fc/fco is 0.8.ltoreq.fc/fco.ltoreq.1.2.
For example, assume that both the frequency fr of the reference signal REF and the center free running frequency fco of the digital VCO 13 are set to 100 MHz and the real center free running frequency fco is 70 MHz. In this case, if the center frequency setting value CFV is set to the maximum value CFVmax, the center frequency fc increases by 20 percent and reaches a value of 84 MHz. In this PLL circuit, because the range of the output frequency f with the change in the digital value DV is 79.8 MHz.ltoreq.f.ltoreq.88.2 MHz. In this PLL circuit, the clock CLK cannot be locked into a phase synchronization state for a reference signal REF of 100 MHz.
As a result, the yield of semiconductor devices becomes low. To improve this yield, a digital VCO 13 with a wide range output frequency f is required. In this case, the digital VCO 13 becomes hard to design and the PLL circuit becomes expensive.
The output clock (feedback clock) CLK is provided to the oscilloscope with the digital value DV fixed to one-half of the maximum value DVmax to measure the output frequency f. The center frequency setting value CFV is adjusted so that the measured output frequency f becomes the reference frequency fr. This adjustment is done manually by an inspector before the semiconductor device is shipped. The center frequency setting circuit 14 is built into the semiconductor device with the PLL circuit and the switch element status is fixed depending on whether or not the fuse not shown in the figure has blown, fixing the center frequency setting value CFV.
In the prior art, such adjustments must be done for each semiconductor chip, slowing down the mass production of semiconductor chips.